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never stop thinking. hys64d64300hu-[5/6/7]-b hys72d64300hu-[5/6/7f]-b hys64d128320hu-[5/6/7]-b hys72d128320hu-[5/6/7f]-b 184-pin unbuffered dual-in-line memory modules udimm ddr sdram data sheet, v0.5, sep. 2003 memory products
edition 2003-09 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2003. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
never stop thinking. hys64d64300hu-[5/6/7]-b hys72d64300hu-[5/6/7f]-b hys64d128320hu-[5/6/7]-b hys72d128320hu-[5/6/7f]-b 184-pin unbuffered dual-in-line memory modules udimm ddr sdram data sheet, v0.5, sep. 2003 memory products
template: mp_a4_v2.0_2003-06-06.fm hys64d64300hu-[5/6/7]-b, hys72d64300hu-[5/6/7f]-b, hys64d128320hu-[5/6/7]-b revision history: v0.5 2003-09 previous version: ? page subjects (major changes since last revision) all new data sheet template we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
data sheet 5 v0.5, 2003-09 hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 current conditions and specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4 spd contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table of contents
data sheet 6 v0.5, 2003-09 184-pin unbuffered dual-i n-line memory modules udimm hys64d64300hu-[5/6/7]-b hys72d64300hu-[5/6/7f]-b hys64d128320hu-[5/6/7]-b hys72d128320hu-[5/6/7f]-b 1 overview 1.1 features 184-pin unbuffered dual-in-line memory modules (ecc and non-parity) for pc and workstation main memory applications one rank 64m x 64, 64m 72 and two ranks 128m 64, 128m 72 organization jedec standard double data rate synchronous drams (ddr sdram) single +2.5v ( 0.2v) power supply built with 512 mbit ddr sdram in p-tsopii-66-1 package programmable cas latency, burst length, and wrap sequence (sequential & interleave) auto refresh (cbr) and self refresh all inputs and outputs sstl_2 compatible serial presence detect with e 2 prom jedec standard mo-206 form factor: 133.35 mm 31.75 mm 4.00 mm max. jedec standard reference layout gold plated contacts ddr400 speed grade supported lead-free 1.2 description the hys64d64300hu-[5/6/7]-b, hys72d64300hu-[5/6/7f]-b, hys64d128320hu-[5/6/7]-b, and hys72d128320hu-[5/6/7f]-b are industry standard 184-pin unbuffered dual-in-line memory modules (udimm) organized as 64m 64, 128m 64 for non-parity and 64m 72,128m 72 for ecc main memory applications. the memory array is designed with 512mbit double data rate synchronous drams. a variety of decoupling capacitors are mounted on the printed circuit board. the dimms feature serial presence detect (spd) based on a serial e 2 prom device using the 2-pin i 2 c protocol. the first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer table 1 performance part number speed code ? 5 ? 6 ? 7 ? 7f unit speed grade component ddr400b ddr333b ddr266a ddr266 ? module pc3200 ?3033 pc2700 ?2533 pc2100 ?2033 pc2100 ?2022 ? max. clock frequency @ cl = 3 f ck3 200 166 ? ? mhz @ cl = 2.5 f ck2.5 166 166 143 143 mhz @ cl = 2 f ck2 133 133 133 133 mhz
data sheet 7 v0.5, 2003-09 hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules overview note: all part numbers end with a place code designating the silicon-die revision. reference information available on request. example: hys72d64300hu-6-b, indicating rev. b dies are used for sdram components. the compliance code is printed on the module labels describing the speed sort (for example ?pc2700?), the latencies and spd code definition (for example ?20330? means cas latency of 2.0 clocks, rcd 1) latency of 3 clocks, row precharge latency of 3 clocks, and jedec spd code definiton version 0), and the raw card used for this module. table 2 ordering information type compliance code description sdram technology pc3200 (cl=3) hys64d64300hu-5-b pc3200u-30330-a0 one rank 512 mb dimm 512 mbit ( 8) hys72d64300hu-5-b pc3200u-30330-a0 one rank 512 mb ecc-dimm 512 mbit ( 8) hys64d128320hu-5-b pc3200u-30330-b0 two ranks 1 gb dimm 512 mbit ( 8) hys72d128320hu-5-b pc3200u-30330-b0 two ranks 1 gb ecc-dimm 512 mbit ( 8) pc2700 (cl=2.5) hys64d64300hu-6-b pc2700u-25330-a0 one rank 512 mb dimm 512 mbit ( 8) hys72d64300hu-6-b pc2700u-25330-a0 one rank 512 mb ecc-dimm 512 mbit ( 8) HYS64D128320HU-6-B pc2700u-25330-b0 two ranks 1 gb dimm 512 mbit ( 8) hys72d128320hu-6-b pc2700u-25330-b0 two ranks 1 gb ecc-dimm 512 mbit ( 8) pc2100 (cl=2) hys64d64300hu-7-b pc2100u-20330-a0 one rank 512 mb dimm 512 mbit ( 8) hys72d64300hu-7f-b pc2100u-20220-a0 one rank 512 mb ecc-dimm 512 mbit ( 8) hys64d128320hu-7-b pc2700u-20330-b0 two ranks 1 gb dimm 512 mbit ( 8) hys72d128320hu-7f-b pc2100u-20220-b0 two ranks 1 gb ecc-dimm 512 mbit ( 8) 1) rcd: row-column-delay
hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules pin configuration data sheet 8 v0.5, 2003-09 2 pin configuration *) for detailed description of the power up and power management on ddr registered dimms see the application note at the end of this datasheet table 3 pin definitions and functions symbol type function a0 ? a11, a12 input address inputs (a12 for 256 mb & 512 mb based modules) ba0, ba1 input bank selects dq0 ? dq63 input/output data input/output cb0 ? cb7 input/output check bits ( 72 organization only) ras , cas , we input command input cke0, cke1 input clock enable dqs0 ? dqs8 input/output sdram low data strobes ck0, ck0 input differential clock input dm0 ? dm8 input sdram low data mask dqs9 ? dqs17 input/output high data strobes cs0 , cs1 input chip selects v dd supply power (+2.5 v) v ss supply ground v ddq supply i/o driver power supply v ddid output v dd indentification flag v ddspd supply eeprom power supply v ref supply i/o reference supply scl input serial bus clock sda output serial bus data line sa0 ? sa2 input slave address select nc input no connect du input don?t use reset input reset pin (forces register inputs low) *)
data sheet 9 v0.5, 2003-09 hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules pin configuration table 4 pin configuration pin# symbol pin# symbol pin# symbol pin# symbol 1 v ref 48 a0 94 dq4 141 a10 2dq0 49cb2 95dq5 142cb6 3 v ss 50 v ss 96 v ddq 143 v ddq 4 dq1 51 cb3 97 dm0/dqs9 144 cb7 5dq0 52ba1 98dq6 key 6dq2 key 99 dq7 145 v ss 7 v dd 53 dq32 100 v ss 146 dq36 8dq3 54 v ddq 101 nc 147 dq37 9 nc 55 dq33 102 nc 148 v dd 10 reset 56 dqs4 103 nc 149 dm4/dqs13 11 v ss 57 dq34 104 v ddq 150 dq38 12 dq8 58 vss 105 dq12 151 dq39 13 dq9 59 ba0 106 dq13 152 v ss 14 dqs1 60 dq35 107 dm1/dqs10 153 dq44 15 v ddq 61 dq40 108 v dd 154 ras 16 du 62 v ddq 109 dq14 155 dq45 17 du 63 we 110 dq15 156 v ddq 18 v ss 64 dq41 111 cke1 157 cs0 19 dq10 65 cas 112 v ddq 158 cs1 20 dq11 66 v ss 113 nc 159 dm5/dqs14 21 dke0 67 dqs5 114 dq20 160 v ss 22 v ddq 68 dq42 115 nc / a12 161 dq46 23 dq16 69 dq43 116 v ss 162 dq47 24 dq17 70 vdd 117 dq21 163 nc 25 dqs2 71 nc 118 a11 164 v ddq 26 v ss 72 dq48 119 dm2/dqs11 165 dq52 27 a9 73 dq49 120 v dd 166 dq53 28 dq18 74 vss 121 dq22 167 nc 29 a7 75 du 122 a8 168 v dd 30 v ddq 76 du 123 dq23 169 dm6/dqs15 31 dq19 77 v ddq 124 v ss 170 dq54 32 a5 78 dqs6 125 a6 171 dq55 33 dq24 79 dq50 126 dq28 172 v ddq 34 v ss 80 dq51 127 dq29 173 nc 35 dq25 81 v ss 128 v ddq 174 dq60 36 dqs3 82 v ddid 129 dm3/dqs12 175 dq61 37 a4 83 dq56 130 a3 176 v ss 38 v dd 84 dq57 131 dq30 177 dm7/dqs16 39 dq26 85 v dd 132 v ss 178 dq62 40 dq27 86 dqs7 133 dq31 179 dq63
hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules pin configuration data sheet 10 v0.5, 2003-09 note: a12 is used for 256mbit and 512mbit based modules only 41 a2 87 dq58 134 cb4 180 v ddq 42 v ss 88 dq59 135 cb5 181 sa0 43 a1 89 v ss 136 v ddq 182 sa1 44 cb0 90 nc 137 ck0 183 sa2 45 cb1 91 sda 138 ck0 184 v ddspd 46 v dd 92 scl 139 v ss ?? 47 dqs8 93 v ss 140 dm8/dqs17 ? ? table 5 address format density organization memory ranks sdrams # of sdrams # of row/bank/ columns bits refresh period interval 512 mb 64m 64 1 64m 8 8 13/2/11 8k 64 ms 7.8 s 512 mb 64m 72 1 64m 8 8 13/2/11 8k 64 ms 7.8 s 1 gb 128m 64 2 64m 8 16 13/2/12 8k 64 ms 7.8 s 1 gb 128m 72 2 64m 8 16 13/2/12 8k 64 ms 7.8 s table 4 pin configuration (cont?d) pin# symbol pin# symbol pin# symbol pin# symbol
data sheet 11 v0.5, 2003-09 hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules pin configuration dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 0 i/o 1 i/o 2 d0 dm0/dqs9 i/o 5 i/o 6 i/o 7 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm i/o 0 i/o 1 i/o 2 i/o 3 d1 i/o 4 i/o 5 i/o 6 dm1/dqs10 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 0 i/o 1 i/o 2 i/o 3 d2 i/o 4 i/o 5 i/o 6 i/o 7 dm2/dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 0 i/o 1 i/o 2 i/o 3 d3 i/o 4 i/o 5 i/o 6 i/o 7 dm3/dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 0 i/o 1 i/o 2 i/o 3 d4 dm4/dqs13 i/o 4 i/o 5 i/o 6 i/o 7 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 0 i/o 1 i/o 2 i/o 3 d5 i/o 4 i/o 5 i/o 6 i/o 7 dm5/dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 0 i/o 1 i/o 2 i/o 3 d6 i/o 4 i/o 5 i/o 6 i/o 7 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 0 i/o 1 i/o 2 i/o 3 d7 i/o 4 i/o 5 i/o 6 i/o 7 dm7/dqs16 a0 - a13 a0-a13: sdrams d0 - d7 a0 serial pd a1 a2 sa0 sa1 sa2 sda ras ras : sdrams d0 - d7 cas cas : sdrams d0 - d7 cke0 cke: sdrams d0 - d7 we we : sdrams d0 - d7 s 0 s s s s s s s s ba0 - ba1 ba0-ba1: sdrams d0 - d7 dqs0 dqs dqs4 dqs1 dqs5 dqs dqs2 dqs dqs3 dqs dm6/dqs15 dqs6 dqs7 dq15 i/o 7 scl dqs dqs dqs dqs * clock wiring *ck0/ck0 clock input sdrams *ck1/ck1 2 sdrams 3 sdrams 3 sdrams * wire per clock loading table/wiring diagrams *ck2/ck2 notes: 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms 5% 4. v ddid strap connections (for memory device v dd , v ddq ): strap out (open): v dd = v ddq strap in (v ss ): v dd v ddq . 5. bax, ax, ras , cas , we resistors: 5.1 ohms + 5% v ss d0 - d7 v dd /v ddq d0 - d7 d0 - d7 v ref v ddid strap: see note 4 wp spd v dd spd dq4 i/o 3 i/o 4 figure 1 block diagram - one rank 64m 64 ddr sdram dimm hys64d64300hu-[5/6/7]-b
hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules pin configuration data sheet 12 v0.5, 2003-09 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 0 i/o 1 i/o 2 i/o 3 d0 dm0/dqs9 dm d8 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm i/o 0 i/o 1 i/o 2 i/o 3 d1 dm d9 i/o 4 i/o 5 i/o 6 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 dm1/dqs10 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 0 i/o 1 i/o 2 i/o 3 d2 dm d10 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm2/dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 0 i/o 1 i/o 2 i/o 3 d3 dm d11 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm3/dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 0 i/o 1 i/o 2 i/o 3 d4 dm4/dqs13 dm d12 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 0 i/o 1 i/o 2 i/o 3 d5 dm d13 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm5/dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 0 i/o 1 i/o 2 i/o 3 d6 dm d14 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 0 i/o 1 i/o 2 i/o 3 d7 dm d15 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm7/dqs16 a0 - a13 a0-a13: sdrams d0 - d15 a0 serial pd a1 a2 sa0 sa1 sa2 sda ras ras : sdrams d0 - d15 cas cas : sdrams d0 - d15 cke0 cke: sdrams d0 - d7 we we : sdrams d0 - d15 s 0 s 1 s s s s s s s s s s s s s s s s cke1 cke: sdrams d8 - d15 ba0 - ba1 ba0-ba1: sdrams d0 - d15 dqs0 dqs dqs4 dqs1 dqs5 dqs dqs dqs2 dqs dqs dqs3 dqs dqs dm6/dqs15 dqs6 dqs7 dq15 i/o 7 i/o 7 dqs dqs dqs dqs dqs dqs dqs dqs dqs * clock wiring *ck0/ck0 clock input sdrams *ck1/ck1 4 sdrams 6 sdrams 6 sdrams * wire per clock loading table/wiring diagrams *ck2/ck2 v ss d0 - d15 v dd /v ddq d0 - d15 d0 - d15 v ref v ddid strap: see note 4 notes: 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms 5%. 4. v ddid strap connections (for memory device v dd , v ddq ): strap out (open): v dd = v ddq strap in (v ss ): v dd v ddq 5. bax, ax, ras , cas , we resistors: 3 ohms + 5% scl wp spd v dd spd figure 2 block diagram - two rank 128m 64 ddr sdram dimm hys64d128320hu-[5/6/7]-b
data sheet 13 v0.5, 2003-09 hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules pin configuration dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 0 i/o 1 i/o 2 i/o 3 d0 dm0/dqs9 i/o 4 i/o 5 i/o 6 i/o 7 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm i/o 0 i/o 1 i/o 2 i/o 3 d1 i/o 4 i/o 5 i/o 6 dm1/dqs10 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 0 i/o 1 i/o 2 i/o 3 d2 i/o 4 i/o 5 i/o 6 i/o 7 dm2/dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 0 i/o 1 i/o 2 i/o 3 d3 i/o 4 i/o 5 i/o 6 i/o 7 dm3/dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 0 i/o 1 i/o 2 i/o 3 d4 dm4/dqs13 i/o 4 i/o 5 i/o 6 i/o 7 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 0 i/o 1 i/o 2 i/o 3 d5 i/o 4 i/o 5 i/o 6 i/o 7 dm5/dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 0 i/o 1 i/o 2 i/o 3 d6 i/o 4 i/o 5 i/o 6 i/o 7 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 0 i/o 1 i/o 2 i/o 3 d7 i/o 4 i/o 5 i/o 6 i/o 7 dm7/dqs16 a0 - a13 a0-a13: sdrams d0 - d8 a0 serial pd a1 a2 sa0 sa1 sa2 sda ras ras : sdrams d0 - d8 cas cas : sdrams d0 - d8 cke0 cke: sdrams d0 - d8 we we : sdrams d0 - d8 s 0 s s s s s s s s ba0 - ba1 ba0-ba1: sdrams d0 - d8 dqs0 dqs dqs4 dqs1 dqs5 dqs dqs2 dqs dqs3 dqs dm6/dqs15 dqs6 dqs7 dq15 i/o 7 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dm i/o 0 i/o 1 i/o 2 i/o 3 d8 i/o 4 i/o 5 i/o 6 i/o 7 s dqs8 dm8/dqs17 dqs dqs dqs dqs dqs * clock wiring *ck0/ck0 clock input sdrams *ck1/ck1 3 sdrams 3 sdrams 3 sdrams * wire per clock loading table/wiring diagrams *ck2/ck2 v ss d0 - d8 v dd /v ddq d0 - d8 d0 - d8 v ref v ddid strap: see note 4 notes: 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms 5%. 4. v ddid strap connections (for memory device v dd , v ddq ): strap out (open): v dd = v ddq strap in (v ss ): v dd v ddq . 5. bax, ax, ras , cas , we resistors: 5.1 ohm + 5% scl wp spd v dd spd figure 3 block diagram - one rank 64m 72 ddr sdram dimm hys72d64300hu-[5/6/7f]-b
hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules pin configuration data sheet 14 v0.5, 2003-09 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 0 i/o 1 i/o 2 i/o 3 d0 dm0/dqs9 dm d9 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm i/o 0 i/o 1 i/o 2 i/o 3 d1 dm d10 i/o 4 i/o 5 i/o 6 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 dm1/dqs10 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 0 i/o 1 i/o 2 i/o 3 d2 dm d11 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm2/dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 0 i/o 1 i/o 2 i/o 3 d3 dm d12 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm3/dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 0 i/o 1 i/o 2 i/o 3 d4 dm4/dqs13 dm d13 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 0 i/o 1 i/o 2 i/o 3 d5 dm d14 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm5/dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 0 i/o 1 i/o 2 i/o 3 d6 dm d15 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 0 i/o 1 i/o 2 i/o 3 d7 dm d16 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm7/dqs16 a0 - a13 a0-a13: sdrams d0 - d17 ras ras : sdrams d0 - d17 cas cas : sdrams d0 - d17 cke0 cke: sdrams d0 - d8 we we : sdrams d0 - d17 s 0 s 1 s s s s s s s s s s s s s s s s * clock wiring *ck0/ck0 clock input sdrams *ck1/ck1 6 sdrams 6 sdrams 6 sdrams cke1 cke: sdrams d9 - d17 * wire per clock loading ba0 - ba1 ba0-ba1: sdrams d0 - d17 dqs0 dqs dqs4 dqs1 dqs5 dqs dqs dqs2 dqs dqs dqs3 dqs dqs dm6/dqs15 dqs6 dqs7 dq15 i/o 7 i/o 7 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dm i/o 0 i/o 1 i/o 2 i/o 3 d8 dm d17 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 s s dqs8 dm8/dqs17 dqs dqs table/wiring diagrams dqs dqs dqs dqs dqs dqs dqs dqs dqs v ss d0 - d17 v dd /v ddq d0 - d17 d0 - d17 v ref *ck2/ck2 v ddid strap: see note 4 notes: 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms 5%. 4. v ddid strap connections (for memory device v dd , v ddq ): strap out (open): v dd = v ddq strap in (v ss ): v dd v ddq 5. bax, ax, ras , cas , we resistors: 3 ohms + 5% a0 serial pd a1 a2 sa0 sa1 sa2 sda scl wp spd v dd spd figure 4 block diagram - two ranks 128m 72 ddr sdram dimm hys72d128320hu-[5/6/7f]-b
data sheet 15 v0.5, 2003-09 hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules pin configuration figure 5 clock net wiring 6 dram loads r = 120 ? 5% dimm connector dram1 dram2 dram3 dram4 dram5 dram6 4 dram loads r = 120 ? 5% dimm connector dram1 dram2 cap. cap. dram5 dram6 3 dram loads r = 120 ? 5% dimm connector dram1 cap. dram3 cap. dram5 cap. 2 dram loads r = 120 ? 5% dimm connector dram1 cap. cap. cap. dram5 cap. 1 dram loads r = 120 ? 5% dimm connector cap. cap. dram3 cap. cap. cap. ck ck cap. = 1/2 ddr sdram input capacitance; 1.0 pf 20%
data sheet 16 v0.5, 2003-09 hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules electrical characteristics 3 electrical characteristics 3.1 operating conditions attention: permanent damage to the device may occur if ?absolute maximum ratings? are exceeded. this is a stress rating only, and functional operation should be restricted to recommended operation conditions. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit. table 6 absolute maximum ratings parameter symbol values unit note/ test condition min. typ. max. voltage on i/o pins relative to v ss v in , v out ?0.5 ? v ddq + 0.5 v? voltage on inputs relative to v ss v in ?1 ? +3.6 v ? voltage on v dd supply relative to v ss v dd ?1 ? +3.6 v ? voltage on v ddq supply relative to v ss v ddq ?1 ? +3.6 v ? operating temperature (ambient) t a 0?+70 c? storage temperature (plastic) t stg -55 ? +150 c? power dissipation (per sdram component) p d ?1?w? short circuit output current i out ?50?ma? table 7 electrical characteristics and dc operating conditions parameter symbol values unit note/test condition 1) min. typ. max. device supply voltage v dd 2.3 2.5 2.7 v f ck 166 mhz device supply voltage v dd 2.5 2.6 2.7 v f ck >166mhz 2) output supply voltage v ddq 2.3 2.5 2.7 v f ck 166 mhz 3) output supply voltage v ddq 2.5 2.6 2.7 v f ck >166mhz 2)3) eeprom supply voltage v ddspd 2.3 2.5 3.6 v ? supply voltage, i/o supply voltage v ss , v ssq 00v? input reference voltage v ref 0.49 v ddq 0.5 v ddq 0.51 v ddq v 4) i/o termination voltage (system) v tt v ref ? 0.04 v ref + 0.04 v 5) input high (logic1) voltage v ih(dc) v ref + 0.15 v ddq + 0.3 v 8) input low (logic0) voltage v il(dc) ?0.3 v ref ? 0.15 v 8) input voltage level, ck and ck inputs v in(dc) ?0.3 v ddq + 0.3 v 8) input differential voltage, ck and ck inputs v id(dc) 0.36 v ddq + 0.6 v 8)6) vi-matching pull-up current to pull-down current vi ratio 0.71 1.4 ? 7)
data sheet 17 v0.5, 2003-09 hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules electrical characteristics input leakage current i i ?2 2 a any input 0 v v in v dd ; all other pins not under test =0v 8)9) output leakage current i oz ?5 5 a dqs are disabled; 0v v out v ddq 8) output high current, normal strength driver i oh ??16.2ma v out = 1.95 v 8) output low current, normal strength driver i ol 16.2 ? ma v out = 0.35 v 8) 1) 0 c t a 70 c 2) ddr400 conditions apply for all clock frequencies above 166 mhz 3) under all conditions, v ddq must be less than or equal to v dd . 4) peak to peak ac noise on v ref may not exceed 2% v ref (dc) . v ref is also expected to track noise variations in v ddq . 5) v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . 6) v id is the magnitude of the difference between the input level on ck and the input level on ck . 7) the ration of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 v. for a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. 8) inputs are not recognized as valid until v ref stabilizes. 9) values are shown per ddr sdram component table 8 ac timing - absolute specifications ?6/?5 parameter symbol ?6 ?5 unit note/ test condition 1) ddr333 ddr400b min. max. min. max. dq output access time from ck/ck t ac ?0.7 +0.7 ?0.6 +0.6 ns 2)3)4)5) dqs output access time from ck/ck t dqsck ?0.6 +0.6 ?0.5 +0.5 ns 2)3)4)5) ck high-level width t ch 0.45 0.55 0.45 0.55 t ck 2)3)4)5) ck low-level width t cl 0.45 0.55 0.45 0.55 t ck 2)3)4)5) clock half period t hp min. ( t cl , t ch )min. ( t cl , t ch )ns 2)3)4)5) clock cycle time t ck 6 12 5 12 ns cl = 3.0 2)3)4)5) 6 12 6 12 ns cl = 2.5 2)3)4)5) 7.5 12 7.5 12 ns cl = 2.0 2)3)4)5) dq and dm input hold time t dh 0.45 ? 0.4 ? ns 2)3)4)5) dq and dm input setup time t ds 0.45 ? 0.4 ? ns 2)3)4)5) control and addr. input pulse width (each input) t ipw 2.2 ? tbd ? ns 2)3)4)5)6) table 7 electrical characteristics and dc operating conditions (cont?d) parameter symbol values unit note/test condition 1) min. typ. max.
data sheet 18 v0.5, 2003-09 hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules electrical characteristics dq and dm input pulse width (each input) t dipw 1.75 ? tbd ? ns 2)3)4)5)6) data-out high-impedance time from ck/ck t hz ?0.7 +0.7 ?0.6 +0.6 ns 2)3)4)5)7) data-out low-impedance time from ck/ ck t lz ?0.7 +0.7 ?0.6 +0.6 ns 2)3)4)5)7) write command to 1 st dqs latching transition t dqss 0.75 1.25 0.75 1.25 t ck 2)3)4)5) dqs-dq skew (dqs and associated dq signals) t dqsq ? +0.40 ? +0.40 ns tfbga 2)3)4)5) ? +0.45 ? +0.40 ns tsopii 2)3)4)5) data hold skew factor t qhs ? +0.50 ? +0.50 ns tfbga 2)3)4)5) ? +0.55 ? +0.50 ns tsopii 2)3)4)5) dq/dqs output hold time t qh t hp ? t qhs ? t hp ? t qhs ?ns 2)3)4)5) dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? t ck 2)3)4)5) dqs falling edge to ck setup time (write cycle) t dss 0.2 ? 0.2 ? t ck 2)3)4)5) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? 0.2 ? t ck 2)3)4)5) mode register set command cycle time t mrd 2?2? t ck 2)3)4)5) write preamble setup time t wpres 0?0?ns 2)3)4)5)8) write postamble t wpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5)9) write preamble t wpre 0.25 ? 0.25 ? t ck 2)3)4)5) address and control input setup time t is 0.75 ? 0.6 ? ns fast slew rate 3)4)5)6)10) 0.8 ? 0.7 ? ns slow slew rate 3)4)5)6)10) address and control input hold time t ih 0.75 ? 0.6 ? ns fast slew rate 3)4)5)6)10) 0.8 ? 0.7 ? ns slow slew rate 3)4)5)6)10) read preamble t rpre 0.9 1.1 0.9 1.1 t ck 2)3)4)5) read postamble t rpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5) active to precharge command t ras 42 70e+3 40 70e+3 ns 2)3)4)5) active to active/auto-refresh command period t rc 60 ? 55 ? ns 2)3)4)5) table 8 ac timing - absolute specifications ?6/?5 (cont?d) parameter symbol ?6 ?5 unit note/ test condition 1) ddr333 ddr400b min. max. min. max.
data sheet 19 v0.5, 2003-09 hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules electrical characteristics auto-refresh to active/auto-refresh command period t rfc 72 ? 65 ? ns 2)3)4)5) active to read or write delay t rcd 18 ? 15 ? ns 2)3)4)5) precharge command period t rp 18 ? 15 ? ns 2)3)4)5) active to autoprecharge delay t rap 18 ? 15 ? ns 2)3)4)5) active bank a to active bank b command t rrd 12 ? 10 ? ns 2)3)4)5) write recovery time t wr 15 ? 15 ? ns 2)3)4)5) auto precharge write recovery + precharge time t dal t ck 2)3)4)5)11) internal write to read command delay t wtr 1?1? t ck 2)3)4)5) exit self-refresh to non-read command t xsnr 75 ? 75 ? ns 2)3)4)5) exit self-refresh to read command t xsrd 200 ? 200 ? t ck 2)3)4)5) average periodic refresh interval t refi ?7.8 ?7.8 s 2)3)4)5)12) 1) 0 c t a 70 c ; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v (ddr333); v ddq = 2.6 v 0.1 v, v dd = +2.6 v 0.1 v (ddr400) 2) input slew rate 1 v/ns for ddr400, ddr333 3) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref . ck/ck slew rate are 1.0 v/ns. 4) inputs are not recognized as valid until v ref stabilizes. 5) the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 6) these parameters guarantee device timing, but they are not necessarily tested on each device. 7) t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 8) the specific requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning from hi-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on t dqss . 9) the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 10) fast slew rate 1.0 v/ns , slow slew rate 0.5 v/ns and < 1 v/ns for command/address and ck & ck slew rate > 1.0 v/ ns, measured between v oh(ac) and v ol(ac) . 11) for each of the terms, if not already an integer, round to the next highest integer. t ck is equal to the actual system clock cycle time. 12) a maximum of eight autorefresh commands can be posted to any given ddr sdram device. table 8 ac timing - absolute specifications ?6/?5 (cont?d) parameter symbol ?6 ?5 unit note/ test condition 1) ddr333 ddr400b min. max. min. max. table 9 ac timing - absolute specifications ?7/?7f parameter symbol ?7 ?7f unit note/ test condition 1) ddr266a ddr266 min. max. min. max. dq output access time from ck/ck t ac ?0.75 +0.75 ?0.75 +0.75 ns 2)3)4)5) dqs output access time from ck/ck t dqsck ?0.75 +0.75 ?0.75 +0.75 ns 2)3)4)5) ck high-level width t ch 0.45 0.55 0.45 0.55 t ck 2)3)4)5)
data sheet 20 v0.5, 2003-09 hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules electrical characteristics ck low-level width t cl 0.45 0.55 0.45 0.55 t ck 2)3)4)5) clock half period t hp min. ( t cl , t ch )min. ( t cl , t ch )ns 2)3)4)5) clock cycle time t ck3 7 12 7 12 ns cl = 3.0 2)3)4)5) t ck2.5 7 12 7 12 ns cl = 2.5 2)3)4)5) t ck2 7.5 12 7.5 12 ns cl = 2.0 2)3)4)5) dq and dm input hold time t dh 0.5 ? 0.5 ? ns 2)3)4)5) dq and dm input setup time t ds 0.5 ? 0.5 ? ns 2)3)4)5) control and addr. input pulse width (each input) t ipw 2.2 ? 2.2 ? ns 2)3)4)5)6) dq and dm input pulse width (each input) t dipw 1.75 ? 1.75 ? ns 2)3)4)5)6) data-out high-impedance time from ck/ck t hz ?0.75 +0.75 ?0.75 +0.75 ns 2)3)4)5)7) data-out low-impedance time from ck/ck t lz ?0.75 +0.75 ?0.75 +0.75 ns 2)3)4)5)7) write command to 1 st dqs latching transition t dqss 0.75 1.25 0.75 1.25 t ck 2)3)4)5) dqs-dq skew (dqs and associated dq signals) t dqsq ?+0.5?+0.5ns 2)3)4)5) data hold skew factor t qhs ? 0.75 ? 0.75 ns 2)3)4)5) dq/dqs output hold time t qh t hp ? t qhs ? t hp ? t qhs ?ns 2)3)4)5) dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? t ck 2)3)4)5) dqs falling edge to ck setup time (write cycle) t dss 0.2 ? 0.2 ? t ck 2)3)4)5) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? 0.2 ? t ck 2)3)4)5) mode register set command cycle time t mrd 2?2? t ck 2)3)4)5) write preamble setup time t wpres 0?0?ns 2)3)4)5)8) write postamble t wpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5)9) write preamble t wpre 0.25 ? 0.25 ? t ck 2)3)4)5) address and control input setup time t is 0.9 ? 0.9 ? ns fast slew rate 3)4)5)6)10) 1.0 ? 1.0 ? ns slow slew rate 3)4)5)6)10) address and control input hold time t ih 0.9 ? 0.9 ? ns fast slew rate 3)4)5)6)10) 1.0 ? 1.0 ? ns slow slew rate 3)4)5)6)10) read preamble t rpre 0.9 1.1 0.9 1.1 t ck 2)3)4)5) read postamble t rpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5) active to precharge command t ras 45 120 e+3 45 120 e+3 ns 2)3)4)5) table 9 ac timing - absolute specifications ?7/?7f (cont?d) parameter symbol ?7 ?7f unit note/ test condition 1) ddr266a ddr266 min. max. min. max.
data sheet 21 v0.5, 2003-09 hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules electrical characteristics active to active/auto-refresh command period t rc 65 ? 60 ? ns 2)3)4)5) auto-refresh to active/auto-refresh command period t rfc 75 ? 75 ? ns 2)3)4)5) active to read or write delay t rcd 20 ? 15 ? ns 2)3)4)5) precharge command period t rp 20 ? 15 ? ns 2)3)4)5) active to autoprecharge delay t rap 20 ? 15 ? ns 2)3)4)5) active bank a to active bank b command t rrd 15 ? 15 ? ns 2)3)4)5) write recovery time t wr 15 ? 15 ? ns 2)3)4)5) auto precharge write recovery + precharge time t dal ( t wr / t ck ) + ( t rp / t ck ) t ck 2)3)4)5)11) internal write to read command delay t wtr 1?1? t ck 2)3)4)5) exit self-refresh to non-read command t xsnr 75 ? 75 ? ns 2)3)4)5) exit self-refresh to read command t xsrd 200 ? 200 ? t ck 2)3)4)5) average periodic refresh interval t refi ? 7.8 ? 7.8 s 2)3)4)5)12) 1) 0 c t a 70 c; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v 2) input slew rate 1 v/ns for ddr400, ddr333, ddr266 3) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref . ck/ck slew rate are 1.0 v/ns. 4) inputs are not recognized as valid until v ref stabilizes. 5) the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 6) these parameters guarantee device timing, but they are not necessarily tested on each device. 7) t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 8) the specific requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning from hi-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on t dqss . 9) the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 10) fast slew rate 1.0 v/ns , slow slew rate 0.5 v/ns and < 1 v/ns for command/address and ck & ck slew rate > 1.0 v/ ns, measured between v oh(ac) and v ol(ac) . 11) for each of the terms, if not already an integer, round to the next highest integer. t ck is equal to the actual system clock cycle time. 12) a maximum of eight autorefresh commands can be posted to any given ddr sdram device. table 9 ac timing - absolute specifications ?7/?7f (cont?d) parameter symbol ?7 ?7f unit note/ test condition 1) ddr266a ddr266 min. max. min. max.
data sheet 22 v0.5, 2003-09 hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules electrical characteristics 3.2 current conditions and specification table 10 i dd conditions parameter symbol operating current 0 one bank; active/ precharge; dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. i dd0 operating current 1 one bank; active/read/precharge; burst length = 4; see component data sheet. i dd1 precharge power-down standby current all banks idle; power-down mode; cke v il,max i dd2p precharge floating standby current cs v ih,,min , all banks idle; cke v ih,min ; address and other control inputs changing once per clock cycle; v in = v ref for dq, dqs and dm. i dd2f precharge quiet standby current cs v ihmin , all banks idle; cke v ih,min ; v in = v ref for dq, dqs and dm; address and other control inputs stable at v ih,min or v il,max . i dd2q active power-down standby current one bank active; power-down mode; cke v ilmax ; v in = v ref for dq, dqs and dm. i dd3p active standby current one bank active; cs v ih,min ; cke v ih,min ; t rc = t ras,max ; dq, dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. i dd3n operating current read one bank active; burst length = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; cl = 2 for ddr266(a), cl = 3 for ddr333 and ddr400b; i out =0ma i dd4r operating current write one bank active; burst length = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; cl = 2 for ddr266(a), cl = 3 for ddr333 and ddr400b i dd4w auto-refresh current t rc = t rfcmin , burst refresh i dd5 self-refresh current cke 0.2 v; external clock on i dd6 operating current 7 four bank interleaving with burst length = 4; see component data sheet. i dd7
data sheet 23 v0.5, 2003-09 hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules electrical characteristics table 11 idd specification and conditions part number & organization hys64d64300hu-7-b hys72d64300hu-7f-b hys64d128320hu-7-b hys72d128320hu-7f-b unit note 1)2) 1) dram component currents only 2) test condition for maximum values: v dd =2.7v, t a =10c 512mb 512mb 1gb 1gb 64 72 64 72 1 rank 1 rank 2 ranks 2 ranks ?7 ?7 ?7 ?7 symbol typ. max. typ. max. typ. max. typ. max. i dd0 600 720 675 810 832 1000 936 1125 ma 3) 3) the module i ddx values are calculated from the component i ddx data sheet values as: m i ddx [component] + n i dd3n [component] with m and n number of components of rank 1 and 2; n =0 for 1 rank modules i dd1 680 800 765 900 912 1080 1026 1215 ma 3)4) 4) dq i/o ( i ddq ) currents are not included into calculations: module i dd values will be measured differently depending on load conditions i dd2p 24 32 27 36 48 64 54 72 ma 5) 5) the module i ddx values are calculated from the corrponent i ddx data sheet values as: ( m + n ) i ddx [component] i dd2f 160 192 180 216 320 384 360 432 ma 5) i dd2q 120 168 135 189 240 336 270 378 ma 5) i dd3p 72 104 81 117 144 208 162 234 ma 5) i dd3n 232 192 261 315 464 560 522 630 ma 5) i dd4r 560 680 630 765 792 960 891 1080 ma 3)4) i dd4w 600 720 675 117 832 384 936 432 ma 3) i dd5 1640 1960 1845 2205 1872 2240 2106 2520 ma 3) i dd6 23 46 26 51 46 91 52 103 ma 5) i dd7 1760 2080 1980 2340 1992 2360 2241 2655 ma 3)4)
data sheet 24 v0.5, 2003-09 hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules electrical characteristics table 12 part number & organization hys64d64300hu-6-b hys72d64300hu-6-b HYS64D128320HU-6-B hys72d128320hu-6-b unit note 1)2) 1) dram component currents only 2) test condition for maximum values: v dd =2.7v, t a =10c 512mb 512mb 1gb 1gb 64 64 64 72 1 rank 1 rank 2 ranks 2 ranks ?6 ?6 ?6 ?6 symbol typ. max. typ. max. typ. max. typ. max. i dd0 720 840 810 945 1000 1168 1125 1314 ma 3) 3) the module i ddx values are calculated from the component i ddx data sheet values as: m i ddx [component] + n i dd3n [component] with m and n number of components of rank 1 and 2; n =0 for 1 rank modules i dd1 760 920 855 1035 1040 1248 1170 1404 ma 3)4) 4) dq i/o ( i ddq ) currents are not included into calculations: module i dd values will be measured differently depending on load conditions i dd2p 24 32 27 36 48 64 54 72 ma 5) 5) the module i ddx values are calculated from the corrponent i ddx data sheet values as: ( m + n ) i ddx [component] i dd2f 200 240 225 270 400 480 450 540 ma 5) i dd2q 136 192 153 216 272 384 306 432 ma 5) i dd3p 88 120 99 135 176 240 198 270 ma 5) i dd3n 280 328 315 369 560 656 630 738 ma 5) i dd4r 680 840 765 945 960 1168 1080 1314 ma 3)4) i dd4w 720 880 810 990 1000 1208 1125 1359 ma 3) i dd5 1760 2120 1980 2385 2040 2448 2295 2754 ma 3) i d d6 46 23 52 27 46 93 52 104 ma 5) dd7 2200 2600 2475 2925 2760 2928 3105 3294 ma 3)4)
data sheet 25 v0.5, 2003-09 hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules electrical characteristics table 13 part number & organization hys64d64300hu-5-b hys72d64300hu-5-b hys64d128320hu-5-b hys72d128320hu-5-b unit note 1)2) 1) dram component currents only 2) test condition for maximum values: v dd =2.7v, t a =10c 512mb 512mb 1 gb 1 gb 64 72 64 72 1 rank 1 rank 2 ranks 2 ranks ?5 ?5 ?5 ?5 symbol typ. max. typ. max. typ. max. typ. max. i dd0 800 920 900 1035 1112 1296 1251 1458 ma 3) 3) the module i ddx values are calculated from the component i ddx data sheet values as: m i ddx [component] + n i dd3n [component] with m and n number of components of rank 1 and 2; n =0 for 1 rank modules i dd1 880 1040 990 1170 1192 1416 1341 1593 ma 3)4) 4) dq i/o ( i ddq ) currents are not included into calculations: module i dd values will be measured differently depending on load conditions i dd2p 24 32 27 36 48 64 54 72 ma 5) 5) the module i ddx values are calculated from the corrponent i ddx data sheet values as: ( m + n ) i ddx [component] i dd2f 240 288 270 324 480 576 540 648 ma 5) i dd2q 152 208 171 234 304 416 342 468 ma 5) i dd3p 96 128 108 144 192 256 216 288 ma 5) i dd3n 312 376 351 423 624 752 702 846 ma 5) i dd4r 800 960 900 1080 1112 1336 1251 1503 ma 3)4) i dd4w 840 1000 945 1125 1152 1376 1296 1548 ma 3) i dd5 1960 2360 2205 2655 2272 2736 2556 3078 ma 3) i d d6 24 47 27 53 48 94 54 106 ma 5) dd7 2480 2920 2790 3285 2792 3296 3141 3708 ma 3)4)
hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules spd contents data sheet 22 v0.5, 2003-09 4 spd contents table 12 spd codes for ?5 part number & organization hys64d64300hu?5?b hys72d64300hu?5?b hys64d128320hu?5?b hys72d128320hu?5?b 512mb 512mb 1gb 1gb 64 72 64 72 1 rank 1 rank 2ranks 2ranks ?5 ?5 ?5 ?5 byte# description hex hex hex hex 0 programmed spd bytes in e2prom 80 80 80 80 1 total number of bytes in e2prom 08 08 08 08 2 memory type ddr-i = 07h 07 07 07 07 3 # of row addresses 0d 0d 0d 0d 4 # number of column addresses 0b 0b 0b 0b 5 # of dimm banks 01 01 02 02 6 data width (lsb) 40 48 40 48 7 data width (msb) 00 00 00 00 8 interface voltage levels 04 04 04 04 9 tck @ clmax (byte 18) [ns] 50 50 50 50 10 tac sdram @ clmax (byte 18) [ns] 50 50 50 50 11 dimm configuration type (non- / ecc) 00 02 00 02 12 refresh rate 82 82 82 82 13 primary sdram width 08 08 08 08 14 error checking sdram width 00 08 00 08 15 tccd [cycles] 01 01 01 01 16 burst length supported 0e 0e 0e 0e 17 number of banks on sdram 04 04 04 04 18 cas latency 1c 1c 1c 1c 19 cs latency 01 01 01 01 20 we (write) latency 02 02 02 02 21 dimm attributes 20 20 20 20 22 component attributes c1 c1 c1 c1 23 tck @ clmax -0.5 (byte 18) [ns] 60 60 60 60 24 tac sdram @ clmax -0.5 [ns] 50 50 50 50 25 tck @ clmax -1 (byte 18) [ns] 75 75 75 75 26 tac sdram @ clmax -1 [ns] 50 50 50 50 27 trpmin (ns) 3c 3c 3c 3c
data sheet 23 v0.5, 2003-09 hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules spd contents 28 trrdmin [ns] 28 28 28 28 29 trcdmin [ns] 3c 3c 3c 3c 30 trasmin [ns] 28 28 28 28 31 module density per bank 80 80 80 80 32 tas, tcs [ns] 60 60 60 60 33 tah, tch [ns] 60 60 60 60 34 tds [ns] 40 40 40 40 35 tdh [ns] 40 40 40 40 36 - 40 not used 00 00 00 00 41 trcmin [ns] 37 37 37 37 42 trfcmin [ns] 41 41 41 41 43 tckmax [ns] 28 28 28 28 44 tdqsqmax [ns] 28 28 28 28 45 tqhsmax [ns] 50 50 50 50 46 - 61 not used 00 00 00 00 62 spd revision 00 00 00 00 63 checksum of byte 0-62 (lsb only) 3e 50 3f 51 64 jedec id code for infineon c1 c1 c1 c1 65 jedec id code for infineon 00 00 00 00 66 jedec id code for infineon 00 00 00 00 67 jedec id code for infineon 00 00 00 00 68 jedec id code for infineon 00 00 00 00 69 jedec id code for infineon 00 00 00 00 70 jedec id code for infineon 00 00 00 00 71 jedec id code for infineon 00 00 00 00 72 module manufacturer location xx xx xx xx 73 part number, char 1 36 37 36 37 74 part number, char 2 34 32 34 32 75 part number, char 3 44 44 44 44 table 12 spd codes for ?5 part number & organization hys64d64300hu?5?b hys72d64300hu?5?b hys64d128320hu?5?b hys72d128320hu?5?b 512mb 512mb 1gb 1gb 64 72 64 72 1 rank 1 rank 2ranks 2ranks ?5 ?5 ?5 ?5 byte# description hex hex hex hex
hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules spd contents data sheet 24 v0.5, 2003-09 76 part number, char 4 36 36 31 31 77 part number, char 5 34 34 32 32 78 part number, char 6 33 33 38 38 79 part number, char 7 30 30 33 33 80 part number, char 8 30 30 32 32 81 part number, char 9 48 48 30 30 82 part number, char 10 55 55 48 48 83 part number, char 11 35 35 55 55 84 part number, char 12 42 42 35 35 85 part number, char 13 20 20 42 42 86 part number, char 14 20 20 20 20 87 part number, char 15 20 20 20 20 88 part number, char 16 20 20 20 20 89 part number, char 17 20 20 20 20 90 part number, char 18 20 20 20 20 91 module revision code xx xx xx xx 92 test program revision code xx xx xx xx 93 module manufacturing date year xx xx xx xx 94 module manufacturing date week xx xx xx xx 95 module serial number xx xx xx xx 96 module serial number xx xx xx xx 97 module serial number xx xx xx xx 98 module serial number xx xx xx xx 99 -127 not used 0 0 0 0 table 12 spd codes for ?5 part number & organization hys64d64300hu?5?b hys72d64300hu?5?b hys64d128320hu?5?b hys72d128320hu?5?b 512mb 512mb 1gb 1gb 64 72 64 72 1 rank 1 rank 2ranks 2ranks ?5 ?5 ?5 ?5 byte# description hex hex hex hex
data sheet 25 v0.5, 2003-09 hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules spd contents table 13 spd codes for ?6 part number & organization hys64d64300hu?6?b hys72d64300hu?6?b hys64d128320hu?6?b hys72d128320hu?6?b 512mb 512mb 1gb 1gb 64 72 64 72 1 rank 1 rank 2ranks 2ranks ?6 ?6 ?6 ?6 byte# description hex hex hex hex 0 programmed spd bytes in e2prom 80 80 80 80 1 total number of bytes in e2prom 08 08 08 08 2 memory type ddr-i = 07h 07 07 07 07 3 # of row addresses 0d 0d 0d 0d 4 # number of column addresses 0b 0b 0b 0b 5 # of dimm banks 01 01 02 02 6 data width (lsb) 40 48 40 48 7 data width (msb) 00 00 00 00 8 interface voltage levels 04 04 04 04 9 tck @ clmax (byte 18) [ns] 60 60 60 60 10 tac sdram @ clmax (byte 18) [ns] 70 70 70 70 11 dimm configuration type (non- / ecc) 00 02 00 02 12 refresh rate 82 82 82 82 13 primary sdram width 08 08 08 08 14 error checking sdram width 00 08 00 08 15 tccd [cycles] 01 01 01 01 16 burst length supported 0e 0e 0e 0e 17 number of banks on sdram 04 04 04 04 18 cas latency 0c 0c 0c 0c 19 cs latency 01 01 01 01 20 we (write) latency 02 02 02 02 21 dimm attributes 20 20 20 20 22 component attributes c1 c1 c1 c1 23 tck @ clmax -0.5 (byte 18) [ns] 75 75 75 75 24 tac sdram @ clmax -0.5 [ns] 70 70 70 70
hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules spd contents data sheet 26 v0.5, 2003-09 25 tck @ clmax -1 (byte 18) [ns] 00 00 00 00 26 tac sdram @ clmax -1 [ns] 00 00 00 00 27 trpmin (ns) 48 48 48 48 28 trrdmin [ns] 30 30 30 30 29 trcdmin [ns] 48 48 48 48 30 trasmin [ns] 2a 2a 2a 2a 31 module density per bank 80 80 80 80 32 tas, tcs [ns] 75 75 75 75 33 tah, tch [ns] 75 75 75 75 34 tds [ns] 45 45 45 45 35 tdh [ns] 45 45 45 45 36 - 40 not used 00 00 00 00 41 trcmin [ns] 3c 3c 3c 3c 42 trfcmin [ns] 48 48 48 48 43 tckmax [ns] 30 30 30 30 44 tdqsqmax [ns] 2d 2d 2d 2d 45 tqhsmax [ns] 55 55 55 55 46 - 61 not used 00 00 00 00 62 spd revision 00 00 00 00 63 checksum of byte 0-62 (lsb only) 42 54 43 55 64 jedec id code for infineon c1 c1 c1 c1 65 jedec id code for infineon 00 00 00 00 66 jedec id code for infineon 00 00 00 00 67 jedec id code for infineon 00 00 00 00 68 jedec id code for infineon 00 00 00 00 69 jedec id code for infineon 00 00 00 00 70 jedec id code for infineon 00 00 00 00 71 jedec id code for infineon 00 00 00 00 72 module manufacturer location xx xx xx xx table 13 spd codes for ?6 part number & organization hys64d64300hu?6?b hys72d64300hu?6?b hys64d128320hu?6?b hys72d128320hu?6?b 512mb 512mb 1gb 1gb 64 72 64 72 1 rank 1 rank 2ranks 2ranks ?6 ?6 ?6 ?6 byte# description hex hex hex hex
data sheet 27 v0.5, 2003-09 hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules spd contents 73 part number, char 1 36 37 36 37 74 part number, char 2 34 32 34 32 75 part number, char 3 44 44 44 44 76 part number, char 4 36 36 31 31 77 part number, char 5 34 34 32 32 78 part number, char 6 33 33 38 38 79 part number, char 7 30 30 33 33 80 part number, char 8 30 30 32 32 81 part number, char 9 48 48 30 30 82 part number, char 10 55 55 48 48 83 part number, char 11 36 36 55 55 84 part number, char 12 42 42 36 36 85 part number, char 13 20 20 42 42 86 part number, char 14 20 20 20 20 87 part number, char 15 20 20 20 20 88 part number, char 16 20 20 20 20 89 part number, char 17 20 20 20 20 90 part number, char 18 20 20 20 20 91 module revision code xx xx xx xx 92 test program revision code xx xx xx xx 93 module manufacturing date year xx xx xx xx 94 module manufacturing date week xx xx xx xx 95 module serial number xx xx xx xx 96 module serial number xx xx xx xx 97 module serial number xx xx xx xx 98 module serial number xx xx xx xx 99 - 127 not used 0 0 0 0 table 13 spd codes for ?6 part number & organization hys64d64300hu?6?b hys72d64300hu?6?b hys64d128320hu?6?b hys72d128320hu?6?b 512mb 512mb 1gb 1gb 64 72 64 72 1 rank 1 rank 2ranks 2ranks ?6 ?6 ?6 ?6 byte# description hex hex hex hex
hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules spd contents data sheet 28 v0.5, 2003-09 table 14 spd codes for ?7/?7f part number & organization hys64d64300hu?7?b hys72d64300hu?7f?b hys64d128320hu?7?b hys72d128320hu?7f?b 512mb 512mb 1gb 1gb 64 72 64 72 1 rank 1 rank 2ranks 2ranks ?7 ?7f ?7 ?7f byte# description hex hex hex hex 0 programmed spd bytes in e2prom 80 80 80 80 1 total number of bytes in e2prom 08 08 08 08 2 memory type ddr-i = 07h 07 07 07 07 3 # of row addresses 0d 0d 0d 0d 4 # number of column addresses 0b 0b 0b 0b 5 # of dimm banks 01 01 02 02 6 data width (lsb) 40 48 40 48 7 data width (msb) 00 00 00 00 8 interface voltage levels 04 04 04 04 9 tck @ clmax (byte 18) [ns] 70 70 70 70 10 tac sdram @ clmax (byte 18) [ns] 75 75 75 75 11 dimm configuration type (non- / ecc) 00 02 00 02 12 refresh rate 82 82 82 82 13 primary sdram width 08 08 08 08 14 error checking sdram width 00 08 00 08 15 tccd [cycles] 01 01 01 01 16 burst length supported 0e 0e 0e 0e 17 number of banks on sdram 04 04 04 04 18 cas latency 0c 0c 0c 0c 19 cs latency 01 01 01 01 20 we (write) latency 02 02 02 02 21 dimm attributes 20 20 20 20 22 component attributes c1 c1 c1 c1 23 tck @ clmax -0.5 (byte 18) [ns] 75 75 75 75 24 tac sdram @ clmax -0.5 [ns] 75 75 75 75 25 tck @ clmax -1 (byte 18) [ns] 00 00 00 00 26 tac sdram @ clmax -1 [ns] 00 00 00 00 27 trpmin (ns) 50 3c 50 3c
data sheet 29 v0.5, 2003-09 hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules spd contents 28 trrdmin [ns] 3c 3c 3c 3c 29 trcdmin [ns] 50 3c 50 3c 30 trasmin [ns] 2d 2d 2d 2d 31 module density per bank 80 80 80 80 32 tas, tcs [ns] 90 90 90 90 33 tah, tch [ns] 90 90 90 90 34 tds [ns] 50 50 50 50 35 tdh [ns] 50 50 50 50 36 not used 00 00 00 00 37 not used 00 00 00 00 38 not used 00 00 00 00 39 not used 00 00 00 00 40 not used 00 00 00 00 41 trcmin [ns] 41 3c 41 3c 42 trfcmin [ns] 4b 4b 4b 4b 43 tckmax [ns] 30 30 30 30 44 tdqsqmax [ns] 32 32 32 32 45 tqhsmax [ns] 75 75 75 75 46 - 61 not used 00 00 00 00 62 spd revision 00 00 00 00 63 checksum of byte 0-62 (lsb only) f4 d9 f5 da 64 jedec id code for infineon c1 c1 c1 c1 65 jedec id code for infineon 00 00 00 00 66 jedec id code for infineon 00 00 00 00 67 jedec id code for infineon 00 00 00 00 68 jedec id code for infineon 00 00 00 00 69 jedec id code for infineon 00 00 00 00 70 jedec id code for infineon 00 00 00 00 71 jedec id code for infineon 00 00 00 00 table 14 spd codes for ?7/?7f part number & organization hys64d64300hu?7?b hys72d64300hu?7f?b hys64d128320hu?7?b hys72d128320hu?7f?b 512mb 512mb 1gb 1gb 64 72 64 72 1 rank 1 rank 2ranks 2ranks ?7 ?7f ?7 ?7f byte# description hex hex hex hex
hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules spd contents data sheet 30 v0.5, 2003-09 72 module manufacturer location xx xx xx xx 73 part number, char 1 36 37 36 37 74 part number, char 2 34 32 34 32 75 part number, char 3 44 44 44 44 76 part number, char 4 36 36 31 31 77 part number, char 5 34 34 32 32 78 part number, char 6 33 33 38 38 79 part number, char 7 30 30 33 33 80 part number, char 8 30 30 32 32 81 part number, char 9 48 48 30 30 82 part number, char 10 55 55 48 48 83 part number, char 11 37 37 55 55 84 part number, char 12 42 46 37 37 85 part number, char 13 20 42 42 46 86 part number, char 14 20 20 20 42 87 part number, char 15 20 20 20 20 88 part number, char 16 20 20 20 20 89 part number, char 17 20 20 20 20 90 part number, char 18 20 20 20 20 91 module revision code xx xx xx xx 92 test program revision code xx xx xx xx 93 module manufacturing date year xx xx xx xx 94 module manufacturing date week xx xx xx xx 95 module serial number xx xx xx xx 96 module serial number xx xx xx xx 97 module serial number xx xx xx xx 98 module serial number xx xx xx xx 99 - 127 not used 0 0 0 0 table 14 spd codes for ?7/?7f part number & organization hys64d64300hu?7?b hys72d64300hu?7f?b hys64d128320hu?7?b hys72d128320hu?7f?b 512mb 512mb 1gb 1gb 64 72 64 72 1 rank 1 rank 2ranks 2ranks ?7 ?7f ?7 ?7f byte# description hex hex hex hex
data sheet 31 v0.5, 2003-09 hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules package outlines 5 package outlines figure 6 raw card a ddr udimm hys64d64300hu-[5/6/7]-b (1 rank module) 92 1 1.27 1 0.05 0.1 b a c detail of contacts 0.2 3 min. 2.5 0.2 3.8 93 0.13 0.1 1.8 a 0.1 c b 17.8 10 184 92 1.27 0.1 c 0.4 b 31.75 0.13 2.7 max. 6.62 0.1 1 2.36 64.77 95 x c b a ?0.1 6.35 120.65 1.27 = 2.175 49.53 92 0.1 4 0.1 a bc 128.95 133.35 b 0.15 a c a burr max. 0.4 allowed l-dim-184-32
hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules package outlines data sheet 32 v0.5, 2003-09 figure 7 raw card a ddr udimm hys72d64 300hu-[5/6/7f]-b (1 rank module) 1 92 0.13 1 0.05 1.27 0.1 b a c detail of contacts 0.2 3 min. 3.8 93 2.5 0.2 1.8 0.1 c a 0.1 b 17.8 184 10 4 0.1 0.1 ac b 128.95 a 133.35 2.7 max. 0.15 b a c 6.35 0.1 2.36 1 64.77 ?0.1 c a b 1.27 x 95 120.65 = 2.175 6.62 49.53 92 b 0.13 31.75 1.27 c 0.1 0.4 1) burr max. 0.4 allowed 1) on ecc modules only l-dim-184-30
data sheet 33 v0.5, 2003-09 hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules package outlines figure 8 raw card b ddr udimm hys64d128320hu-[5/6/7]-b (2 ranks module) 4 c b 0.1 a 0.1 2.36 1 0.1 c 64.77 ?0.1 a b 95 133.35 128.95 1.27 x= 2.175 6.62 120.65 a 6.35 1.27 0.15 4 max. 49.53 92 0.4 31.75 b 0.13 c b 0.1 a c 0.1 detail of contacts 0.2 1.27 3.8 0.13 3 min. 93 0.2 2.5 1 0.05 0.1 ac b 1.8 0.1 b a c 184 10 17.8 burr max. 0.4 allowed l-dim-184-33
hys[64/72]d[64300/128320]hu-[5/6/7/7f]-b unbuffered ddr sdram modules package outlines data sheet 34 v0.5, 2003-09 figure 9 raw card b ddr udimm hys72d128320hu-[5/6/7/-b (2 rank module) 1 1 92 92 0.1 1.27 c 4 max. 0.4 a 0.1 b c a 133.35 128.95 a 0.15 b c 0.1 4 b 0.13 31.75 a 64.77 2.36 0.1 ?0.1 6.35 95 x 1.27 = 120.65 6.62 c b 2.175 49.53 0.05 1 1.27 0.2 detail of contacts 0.1 abc 2.5 0.2 17.8 10 184 93 0.13 3.8 3 min. 0.1 1.8 b a 0.1 c 1) burr max. 0.4 allowed 1) on ecc modules only l-dim-184-31
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